1. Field of the Invention
The present invention relates to a memory device and a memory device controlling apparatus.
2. Description of Related Art
A memory device contains a semiconductor memory element capable of storing data. A memory device controlling apparatus can be connected to a memory device. The memory device controlling apparatus is capable of writing data onto a memory device and reading data therefrom.
Conventional memory device and memory device controlling apparatus include buses respectively. The bus of the memory device and the bus of the memory device controlling apparatus are operated at different speeds.
JP 2006-195948 A discloses bus bridges enabling the transfer of data between buses operated at different speeds. The bus bridges are adaptable to a plurality of various frequencies and connected in parallel between the buses. The selection of a bus bridge depending upon the relationship between clock frequencies of both the buses enables data to be transferred between two different buses even when the buses are operated at different speeds.
FIG. 25 is a block diagram of conventional memory device and memory device controlling apparatus. A host PC 101 is an information processing apparatus typified by a personal computer or the like. A memory device 103 contains a non-volatile memory such as a flash memory. An adaptor 102 is capable of connecting the host PC 101 to the memory device 103. The adaptor 102 includes a first bus bridge 2221, a second bus bridge 2222, a third bus bridge 2223, a fourth bus bridge 2224, a first selecting part 2231, and a second selecting part 2232. The first bus bridge 2221, the second bus bridge 2222, the third bus bridge 2223, and the fourth bus bridge 2224 are operated respectively at different frequencies. The first selecting part 2231 is capable of selecting a bus bridge in accordance with the operation frequency of the host PC 101. The second selecting part 2232 is capable of selecting a bus bridge in accordance with the operation frequency of the memory device 103.
However, the memory device and the memory device controlling apparatus shown in FIG. 25 cannot be operated in an optimum operation mode in accordance with the characteristics of each bus, the host PC 101, and the memory device 103.